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Cypress Semiconductor /psoc63 /SRSS /SRSS_INTR_CFG

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Interpret as SRSS_INTR_CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)HVLVD1_EDGE_SEL

HVLVD1_EDGE_SEL=DISABLE

Description

SRSS Interrupt Configuration Register

Fields

HVLVD1_EDGE_SEL

Sets which edge(s) will trigger an IRQ for HVLVD1

0 (DISABLE): Disabled

1 (RISING): Rising edge

2 (FALLING): Falling edge

3 (BOTH): Both rising and falling edges

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data