Cypress Semiconductor /psoc63 /SRSS /SRSS_INTR_CFG

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Interpret as SRSS_INTR_CFG

31282724232019161512118743000000000000000000000000000000000000000000 (DISABLE)HVLVD1_EDGE_SEL

HVLVD1_EDGE_SEL=DISABLE

Description

SRSS Interrupt Configuration Register

Fields

HVLVD1_EDGE_SEL

Sets which edge(s) will trigger an IRQ for HVLVD1

0 (DISABLE): Disabled

1 (RISING): Rising edge

2 (FALLING): Falling edge

3 (BOTH): Both rising and falling edges

Links

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